Memory access control device

ABSTRACT

A memory access control system is provided which is made up of a memory master to make a request for access to memory, a memory control section to produce control signals of memories based on access information and a hit predicting section to predict whether next access to each bank in memory is gotten to a same page (page hit is found) wherein the memory control section, when the hit predicting section predicts that a page hit is found, terminates its routine without closing the bank being presently accessed at time of completion of present access operations and, when the hit predicting section predicts that a miss hit is found, closes a bank being presently accessed and terminates its routine.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a memory access control device to be employed in a DRAM (Dynamic Random Access Memory) such as an SDRAM (Synchronous DRAM), DDR (Double Data Rate) —SDRAM and more particularly to the memory access control device being capable of enhancing access performance by predicting whether or not a page hit is found.

[0003] The present application claims priority of Japanese Patent Application No. 2003-084790 filed on Mar. 26, 2003, which is hereby incorporated by reference.

[0004] 2. Description of the Related Art

[0005] A conventional memory access control method is either of an open page policy in which, when access to a DRAM is completed, a routine is terminated without pre-charging an accessed bank or of a closed page policy in which, a routine is terminated after the accessed bank has been pre-charged.

[0006] If a bank is in a state where the bank has been already pre-charged and closed, the same bank, when being accessed next time, can be accessed at a constant speed regardless of its address. However, in a case where a bank has not been pre-charged but has been opened, if a same page as its bank has been opened is to be accessed, since opening of the page is not required, the bank can be accessed speedily when compared with the case where the bank has been closed. However, when a page being different from a page whose bank has been opened is to be accessed, since the page to which access is gotten has to be opened after the bank has been pre-charged, the bank can be accessed at a slower speed when compared with the case where the bank has been closed.

[0007] Access to a same page is called a “page hit” and access to a different page is called a “miss hit (mishit)”.

[0008] A memory control device employing a conventional open page policy is disclosed in which access efficiency is improved by changing timing with which a bank is closed according to the number of times of page-hit accesses to a bank (Japanese Patent Application Laid-open No. 2001-166985).

[0009] Both the closed page policy and open page policy have problems. That is, the closed page policy heightens access performance when a probability of a page hit is low, while the open page policy heightens the access performance when a probability of the page hit is high. However, neither the closed page policy nor the open page policy cannot make the access performance reach its theoretical limit.

[0010] The conventional memory control device has a problem. That is, in the memory control device employing the open page policy in which timing with which a bank is closed is changed according to the number of times of page hit accesses to a bank, since the bank is always kept opened, after access has been gotten, until shortest timing with which a bank is closed, if access by which a miss hit is found is gotten continuously at a short interval, the access efficiency is not improved.

[0011] Moreover, the conventional memory control device also has a problem. That is, when the shortest timing with which a bank is closed is set to be shorter than an interval for access to a memory, since the operation becomes the same as in the case of the closed page policy, if many page hits are found, there is no improvement of access efficiency.

SUMMARY OF THE INVENTION

[0012] In view of the above, it is an object of the present invention to provide a memory access control device being capable of enhancing memory access efficiency by predicting whether or not a page hit is found in subsequent access.

[0013] According to a first aspect of the present invention, there is provided a memory access control device including:

[0014] a memory master to make a request for access to memory;

[0015] a memory control unit to produce control signals of memories based on access information to be output from the memory master; and

[0016] a hit predicting unit to predict whether or not next access to each bank in memory becomes access to a same page;

[0017] wherein the memory control unit, when a hit predicting unit predicts that next access to the bank becomes access to a same page, that is, that a page hit is found, terminates its routine without closing a bank being presently accessed at time of completion of present access operations and, when the hit predicting unit predicts that next access to the bank becomes access to a different page, that is, that a miss hit (mishit) is found, closes the bank being presently accessed at time of completion of present access operations and terminates its routine.

[0018] In the foregoing, a preferable mode is one wherein the hit predicting unit stores results from recent (last) “n” (“n” is a natural number) times accesses to each bank in memory as to whether a page hit has been found or a miss hit has been found and predicts, if a number of times of accesses by which a page hit is found out of recent “n” times accesses is “m” or more (m≦n: “m” and “n” each are a natural number), that a page hit is found in next access to the bank and predicts, if the number of times of accesses is not “m” or more, that a miss hit is found in next access to the bank.

[0019] Also, a preferable mode is one wherein the hit predicting unit stores results from recent “j” (“j” is a natural number) times accesses to each bank in memory as to whether a page hit has been found or a miss hit has been found and predicts, when a page hit has been found in all recent “j” times accesses, that a page hit is found in next access to the bank and predicts, if no page hit has been found in all recent “j” times accesses, that a miss hit is found in next access to the bank.

[0020] Also, a preferable mode is one wherein the hit predicting unit stores results from recent “k” (“k” is a natural number) times accesses to each bank in memory as to whether a page hit has been found or a miss hit has been found and predicts, if a miss hit has been found in all recent “k” times accesses, that a miss hit is found in next access to the bank and predicts, if no miss hit has been found in all recent “k” times accesses, that a miss hit is found in next access to the bank.

[0021] Also, a preferable mode is one wherein the hit predicting unit stores results from recent “k” (“k” is a natural number) times accesses to each bank in memory as to whether a page hit has been found or a miss hit has been found and predicts, when a miss hit has been found in all recent “k” times accesses out of recent n times accesses, that a miss hit is found in next access to the bank and predicts, when no miss hit has been found in all recent “k” times accesses out of recent “n” times accesses, if a page hit is found in recent “j” times accesses (j≦n: “j” and “n” each are a natural number) out of recent “n” times accesses, that a page hit is found in next access to the bank and predicts, when a miss hit has been found in all recent “j” times accesses out of recent “n” times accesses, if a number of times of accesses by which a page hit has been found out of recent “n” times accesses is “m” times or more (m≦n: “m” and “n” each are a natural number), that a page hit is found in next access to the bank and predicts, when a number of times of accesses by which a page hit has been found out of recent “n” times accesses is not “m” times or more, that a miss hit is found in next access to the bank.

[0022] Furthermore, a preferable mode is one wherein the memory master informs, when a bank and a page to be accessed next have been determined, the memory control unit of information about the bank and the page to be accessed and wherein the memory control unit, if the bank to be accessed next by the memory master is same as that being presently accessed and the page to be accessed by the memory master is same as that being presently accessed, terminates its routine, regardless of a prediction result from the hit predicting unit, without closing the bank being presently accessed at time of completion of present access operations and, when the memory control unit does not terminate its routine, if the bank to be accessed next by the memory master is same as that being presently accessed and the page to be accessed by the memory master is different from that being presently accessed, closes the bank being presently accessed at time of completion of present access operations, regardless of a prediction result from the hit predicting unit, and terminates its routine.

[0023] According to a second aspect of the present invention, there is provided a memory access control device including:

[0024] two or more memory masters to make a request for access to memory;

[0025] an arbiter unit to arbitrate memory access requests fed from the memory masters and to select access information fed from any one of the memory masters;

[0026] a memory control unit to produce a control signal of memory based on access information output from the arbiter unit; and

[0027] a hit predicting unit to predict whether or not next access to each bank in memory becomes access to a same page;

[0028] wherein the memory control unit, when the hit predicting unit predicts that next access to the bank is access to a same page, that is, a page hit is found, terminates its routine without closing the bank being presently accessed at time of completion of present access operations and when the hit predicting unit predicts that next access to the bank is access to a different page, that is, that a miss hit is found, closes the bank being presently accessed at time of present access operations and terminates its routine.

[0029] In the foregoing, a preferable mode is one wherein the hit predicting unit stores results from recent “n” (“n” is a natural number) times accesses to each bank in memory as to whether a page hit has been found or a miss hit has been found and predicts, if a number of accesses by which a page hit is found out of recent “n” times accesses is “m” or more (m≦n: “m” and “n” each are a natural number), that a page hit is found in next access to the bank and predicts, if the number of times of accesses is not “m” or more, that a miss hit is found in next access to the bank.

[0030] Also, a preferable mode is one wherein the hit predicting unit stores results from recent “j” (“j” is a natural number) times accesses to each bank in memory as to whether a page hit has been found or a miss hit has been found and predicts, when a page hit has been found in all recent “j” times accesses, that a page hit is found in next access to the bank and predicts, if no page hit has been found in all recent “j” times accesses, that a miss hit is found in next access to the bank.

[0031] Also, a preferable mode is one wherein the hit predicting unit stores results from recent “k” (“k” is a natural number) times accesses to each bank in memory as to whether a page hit has been found or a miss hit has been found and predicts, if a miss hit has been found in all recent “k” times accesses, that a miss hit is found in next access to the bank and predicts, if no miss hit has been found in all recent “k” times accesses, that a page hit is found in next access to the bank.

[0032] Also, a preferable mode is one wherein the hit predicting unit stores results from recent “n” (“n” is a natural number) times accesses to each bank in memory as to whether a page hit has been found or a miss hit has been found and predicts, when a miss hit has been found in all recent “k” (k≦n: “k” and “n” each are a natural number) times accesses out of recent “n” times accesses, that a miss hit is found in next access to the bank and predicts, when no miss hit has been found in all recent “k” times accesses out of recent “n” times accesses, if a page hit is found in all recent “j” times accesses (j≦n: “j” and “n” each are a natural number) out of recent “n” times accesses, that a page hit is found in next access to the bank and predicts, when a miss hit has been found in all recent “k” times accesses out of recent “n” times accesses, if a number of times of accesses by which a page hit has been found out of recent “n” times accesses is “m” times or more (m≦n: “m” and “n” each are a natural number), that a page hit is found in next access to the bank and predicts, when a number of times of accesses by which a page hit has been found out of recent “n” times accesses is not “m” times or more, that a miss hit is found in next access to the bank.

[0033] Furthermore, a preferable mode is one wherein each memory master informs, when a bank and a page to be accessed next have been determined, the arbiter unit and the memory control unit of information about the bank and the page to be accessed and wherein the memory control unit, if there exists the memory master which gets next access to a same bank as that being presently accessed and to a same page as that being presently accessed, closes the bank being presently accessed at time of completion of present access operations, regardless of a prediction result fed from the hit predicting unit, and terminates its routine and, when not terminating its routine, if there exists the memory master which gets next access to a same bank as that being presently accessed and to a page being different from that being presently accessed, closes the bank being presently accessed at time of completion of present access operations, regardless of a prediction result fed from a hit predicting unit, and terminates its routine and the arbiter unit, if there exists the memory master which gets next access to a same bank and a same page as those being presently accessed, selects said memory master with priority.

[0034] With the above configuration, when access is gotten to a same bank next time, if a page hit is predicted, access is gotten according to an open page policy and if a miss hit is predicted, access is gotten according to a close page policy and therefore when the prediction comes true, performance reaching a theoretical limit can be achieved.

[0035] Moreover, even if the prediction does not come true completely, when a hit rate is 50% or more, since the number of times of decreases in miss hits becomes larger than the number of times of decreases in page hits, a memory access rate is improved.

[0036] Furthermore, when access is gotten, whether an accessed bank is closed or opened is determined by predicting whether a page hit is found in next access and, therefore, even when access in which a miss hit is found occurs in short intervals continuously, access efficiency can be enhanced.

BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The above and other objects, advantages, and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings in which:

[0038]FIG. 1 is a block diagram showing a system made up of a memory access control device and a plurality of memories corresponding to claim 1 of the present invention;

[0039]FIG. 2 is another block diagram showing the system made up of a memory control section and a plurality of memories corresponding to any one of claims 2, 3, 4, and 5 of the present invention;

[0040]FIG. 3 is still another block diagram showing the system made up of the memory control section and a plurality of memories corresponding to claims 6 to 10 of the present invention;

[0041]FIG. 4 is still another block diagram showing a system made up of the memory control section and a plurality of memories corresponding to claim 11 of the present invention;

[0042]FIG. 5 is still another block diagram showing the system made up of a memory control section and a plurality of memories corresponding to anyone of claims 12, 13, 14, and 15 of the present invention;

[0043]FIG. 6 is still another block diagram showing the system made up of a memory control section and a plurality of memories corresponding to claims 16 to 20 of the present invention;

[0044]FIG. 7 is a block diagram showing configurations of one bank installed in a hit predicting section corresponding to claims 5 and 15 of the present intention;

[0045]FIG. 8 is a timechart showing a case in which the memory access control device of the present invention, while getting read-access, predicts a hit in next access and a hit is found in access;

[0046]FIG. 9 is a timechart showing a case in which the memory access control device of the present invention, while getting read-access, predicts a hit in next access and a miss hit is found in access; and

[0047]FIG. 10 is a timechart showing a case in which the memory access control device of the preset invention, while getting read-access, predicts a miss hit in next access.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0048] Best modes of carrying out the present invention will be described in further detail using various embodiments with reference to the accompanying drawings.

[0049]FIG. 1 is a block diagram showing a system made up of a memory control device 3 and a plurality of memories 5 and 6 corresponding to claim 1 of the present invention.

[0050] A memory master 1 outputs a request signal requesting a right of using memory, an address signal, a read/write signal showing types of accesses, a word length signal indicating what number of words is to be accessed to, a write data signal, and a data mask signal to the memory control section 3. The memory master 1 also receives an acknowledge signal and a read data signal indicating acquisition of a memory right from the memory control section 3.

[0051] The memory control section 3 outputs control signals for memory. That is, in the case of an SDRAM, its memory control section 3 outputs a clock signal (CLK), a clock enable signal (CKE), a chip select signal (CS), a row address strobe signal (RAS), a column address strobe signal (CAS), a write enable signal (WE), an address signal (A), a bank address signal (BA), a data input/output signal (DQ), and a data mask signal (DQM).

[0052] A hit predicting section 4 outputs a plurality of hit prediction results to the memory control section 3. The number of hit prediction results is the same as the total number of banks in all memories being connected. For example, if two memories 5 and 6 each being made up of four banks are connected, since an entire system has eight banks, the predict number obtained as the hit prediction results becomes eight.

[0053] The memory master 1, when access to memory is required, asserts a request signal and, at the same time, outputs an address signal, a read/write signal, a word length signal, a write data signal, and a data mask signal in a determined manner.

[0054] The memory control section 3, when the request signal fed from the memory master 1 is asserted, receives the address signal, the read/write signal, and the word length signal and, produces a control signal for memory, if the read/write signal indicates “write access” to get access for writing and, if the read/write signal indicates “read access” to get access for reading.

[0055] The memory control section 3, if the read/write signal indicates “write access”, receives a write data signal and a data mask signal and, if the read/write signal indicates “read access”, returns read data fed back from memories to the memory master 1 by using the read data signal.

[0056] The memory control section 3, when accessing last data, determines whether or not a bank being accessed presently is closed by making a reference to the hit prediction result fed from the hit predicting section 4.

[0057] The above last data, for example, when the word length signal indicates that four words are to be accessed, represents fourth word data.

[0058] Although the hit prediction results fed from the hit predicting section 4, each are corresponding to any one of banks in the memories 5 and 6 in a one-to-one relationship and the memory control section 3 makes a reference to a hit prediction result corresponding to the bank which stores last data.

[0059] Moreover, though the memory control section 3 determines whether or not a bank being presently accessed is closed by making a reference to the bank storing the last data, if next data is stored in a bank being different from the bank being presently accessed, the memory control section 3 determines whether or not the bank being presently accessed is closed by making a reference to the hit prediction result fed from the hit predicting section 4.

[0060]FIG. 2 is also a block diagram showing a system made up of the memory control section 3 and a plurality of memories 5 and 6 corresponding to any one of claims 2, 3, 4, and 5 of the present invention.

[0061] The hit predicting section 4 receives a hit signal or miss hit (mishit) signal from the memory control section 3. Each of the number of hit results and miss hit results is the same as the total number of banks in each of the memories 5 and 6.

[0062] The memory control section 3, since it stores a page address of each bank that was accessed last, if the page address indicates, at time of starting next access, the same page as that having been accessed previous time, asserts a hit signal corresponding to a bank.

[0063] Moreover, the memory control section 3, at time of starting access, if the page address indicates a page being different from the page having been accessed previous time, asserts a miss hit signal corresponding to a bank.

[0064] The time when access is started includes not only time when first access is started after a request signal fed from the memory master 1 has been asserted but also time when next access is started if each of data being presently accessed and data to be accessed next is stored in each of different banks before access to a length of words indicated by a word length signal is completed.

[0065] Next, operations of the hit predicting section 4 corresponding to claim 2 of the present invention. The hit predicting section 4, every time a hit signal or a miss hit signal fed from the memory control section 3 is asserted, stores the result from asserting signals, corresponding to the number of recent (last) “n” (“n” denotes a natural number) times of assertion of the hit signals or the miss hit signals for each bank.

[0066] The hit predicting section 4 judges whether the number of times of asserting hit signals is “m” times or more (m≦n: “m” and “n” are natural numbers) for each bank and outputs, if the number of times of asserting hit signals is “m” times or more, information indicating that a page hit is found as a hit prediction result and outputs, if the number of times of asserting the hit signal is less than “m” times, information indicating that a miss hit is found.

[0067] For example, if “n” is eight and if the hit signals and the miss hit signals from a bank are asserted in order of hit, hit, miss hit, hit, hit, miss hit, hit, and miss hit, since the number of times of asserting hit signals is five in recent eight times asserting operations, if “m” is five or less, a hit prediction result of the bank indicates that a page hit is found and, if “m” is six or more, a hit prediction result of the bank indicates that a miss hit is found.

[0068] Moreover, after this, if a miss hit signal is asserted, the number of times of asserting hit signals is four in recent eight times asserting operations and if not a miss hit signal but a hit signal is asserted, the number of times of asserting hit signals is five and no change occurs. Moreover, “n” is determined at time of system design and “m” is made variable depending on setting.

[0069] Next, operations of the hit predicting section 4 corresponding to claim 3 will be described. The hit predicting section 4, every time a hit signal or a miss hit signal fed from the memory control section 3 is asserted, stores the result of the assertion, corresponding to the number of times of asserting the signals in recent “j” (“j” denotes a natural number) asserting times for each bank.

[0070] The hit predicting section 4 judges whether or not a result from asserting a hit signal or a miss hit signal for each bank indicates that a hit signal is asserted in all recent “j” asserting times operations and, if YES, outputs information indicating that a page hit is found as a corresponding hit prediction result and, if NO, outputs information indicating that a miss hit is found.

[0071] For example, if “j” is four and if the hit signals and the miss hit signals of a bank are asserted in order of miss hit, hit, miss hit, miss hit, hit, hit, hit, and hit, since a hit signal is asserted in all recent four times asserting operations, a hit prediction result of the bank indicates that a page hit is found.

[0072] Moreover, after this, if a miss hit signal is asserted, the number of times of asserting a hit signal is three in recent four times asserting operations, a hit prediction result of the bank indicates that a miss hit is found. If not a miss hit signal but a hit signal is asserted, a hit prediction result of the bank indicates that a page hit remains to be found. Moreover, “j” is made variable depending on setting.

[0073] Next, operations of the hit predicting section 4 corresponding to claim 4 will be described. The hit predicting section 4, every time a hit signal or a miss hit signal fed from the memory control section 3 is asserted, stores the result of assertion, corresponding to the number of times of asserting the signals in recent “k” (“k” denotes a natural number) times asserting operations for each bank.

[0074] The hit predicting section 4 judges whether or not a result from asserting a hit signal or a miss hit signal for each bank indicates that a miss hit signal is asserted in all recent “k” times asserting operations and, if YES, outputs information indicating that a miss hit is found as a corresponding hit prediction result and, if NO, outputs information indicating that a page hit is found.

[0075] For example, if “k” is four and if the hit signals and the miss hit signals from a bank are asserted in order of miss hit, hit, miss hit, hit, miss hit, miss hit, miss hit, and miss hit, since a miss hit signal is asserted in all recent four times asserting operations, a hit prediction result of the bank indicates that a miss hit is found.

[0076] Moreover, after this, if a hit signal is asserted, the number of times of asserting a miss hit signal is three in recent four times asserting operations, a hit prediction result of the bank indicates that a page hit is found. If not a hit signal but a miss hit signal is asserted, a hit prediction result of the bank indicates that a miss hit remains to be found. Moreover, “k” is made variable depending on setting.

[0077] Next, operations of the hit predicting section 4 corresponding to claim 5 will be described. The hit predicting section 4, every time a hit signal or a miss hit signal fed from the memory control section 3 is asserted, stores the result of assertion, corresponding to the number of times of asserting the signals in recent “n” (“n” denotes a natural number) times asserting times for each bank.

[0078] The hit predicting section 4 judges whether or not a result from asserting a hit signal or a miss hit signal for each bank indicates that a miss hit is found in all recent “k” times asserting operations and, if YES, outputs information indicating that a miss hit is found as a hit prediction result (k≦n: “k” and “n” each are a natural number).

[0079] On the other hand, the hit predicting section 4 judges whether or not a result from asserting a hit signal or a miss hit signal for each bank indicates that a page hit is found in all recent “j” times asserting operations and, if YES, outputs information indicating that a page hit is found as a hit prediction result (j≦n: “j” and “n” each are a natural number).

[0080] The hit predicting section 4 judges whether the number of times of asserting a hit signal for each bank is “m” times or more (m≦n: “m” and “n” each are a natural number) in recent “n” times asserting operations and, if the number of times of asserting a hit signal is “m” times or more, outputs information indicating that a page hit is found as a hit prediction result and, outputs, if NOT, information indicating that a miss hit is found.

[0081] For example, if “n” is eight, “k” is four, “j” is four, and “m” is five, and if the hit signals and the miss hit signals from a bank are asserted in order of hit, hit, miss hit, hit, miss hit, miss hit, miss hit, and miss hit, since a miss hit is found in all recent four times asserting operations, a hit prediction result of the bank indicates that a miss hit is found.

[0082] Moreover, if the hit signals and the miss hit signals from a bank are asserted in order of hit, hit, miss hit, miss hit, hit, hit, hit, and hit, since not a miss hit but a hit is found in all recent four times asserting operations, a hit prediction result of the bank indicates that a page hit is found.

[0083] Also, if the hit signals and the miss hit signals from a bank are asserted in order of hit, hit, miss hit, miss hit, hit, hit, hit and miss hit, though a miss hit is not found in all recent four times asserting operations and a hit is not found in all recent four times asserting operations, since a hit is found five times in the recent eight times asserting operations, a hit prediction result of the bank indicates that a page hit is found.

[0084] Furthermore, if the hit signals and the miss hit signals from a bank are asserted in order of miss hit, hit, miss hit, miss hit, hit, hit, hit and miss hit, though a miss hit is not found in all recent four times asserting operations and a hit is not found in all recent four times asserting operations, since a hit is found only four times in the. recent eight times asserting operations, a hit prediction result of the bank indicates that a miss hit is found.

[0085] Moreover, though “n” is determined at time of designing a system, “m”, “j” and “k” are made variable depending on setting.

[0086]FIG. 3 is still another block diagram showing the system made up of the memory control section 3 and a plurality of memories 5 and 6 corresponding to claims 6 to 10 of the present invention.

[0087] In the system shown in FIG. 3, in addition to the embodiment corresponding to claim 1 of the present invention, the memory master 1 outputs a next address signal indicating an address to be used when an access request is made next and a next address confirming signal indicating that the address signal is determined, to the memory control section 3.

[0088] The memory control section 3, when getting access to last data, determines whether or not a bank being presently accessed is closed depending on a hit prediction result fed from the hit predicting section 4. At this point, the memory control section 3, if the memory master 1 outputs a next address confirming signal and when a bank and a page indicated by its next address signal are matched to the bank and the page being presently accessed, terminates its routine without closing a bank being presently accessed, regardless of a hit prediction result fed from the hit predicting section 4.

[0089] On the other hand, the memory control section 3, while the memory master 1 outputs an address confirming signal and if only the bank out of the bank and the page indicated by its address signal is matched to the bank out of the bank and the page being presently accessed and if the page out of the bank and the page indicated by its address signal is not matched to the page out of the bank and the page being presently accessed, closes the bank being presently accessed and terminates its routine, regardless of a hit prediction result fed from the hit predicting section 4.

[0090] For example, let it be assumed that the memory master 1 is now getting access to a bank and a page and its last address is a bank 0 and a page 0. If the memory master 1 has asserted a next address confirming signal and if both a bank and a page indicated by a next address signal fed from the memory master 1 are 0, the memory control section 3, terminates its routine without closing the bank 0 at time when the memory master 1 completes its access, regardless of a hit prediction result fed from the hit predicting section 4.

[0091] Though the memory master 1 accesses the bank 0 and page 0 next, since the bank 0 has been opened at page 0, the memory master 1 can start next access immediately after the previous access is completed.

[0092] If the bank 0 has been closed at time when the memory master 1 completes its access, access to memory has to be started after having made the bank 0 active and time is spent before next access to memory is started.

[0093] Also, if the bank and the page indicated by a next address signal fed from the memory master 1 are 0 and 1 respectively, the memory control section 3, closes the bank 0 and terminates its routine at time when the memory master 1 completes access, regardless of a hit prediction result fed from the hit predicting section 4.

[0094] Though the memory master 1 next gets access to the bank 0 in memory, since the bank 0 has been closed, after previous access by the memory master 1 has been completed, the bank 0 is immediately made active and after the bank 0 has been made active, memory can be accessed.

[0095] If the bank 0 has not been closed when the previous access by the memory master 1 is completed, the bank 0 has to be made active after the bank 0 has been pre-charged following the completion of previous access by the memory master 1 and therefore time is spend before next access to memory is started.

[0096]FIG. 4 is a block diagram showing a system made up of a memory control section 3 and a plurality of memories 5 and 6 corresponding to claim 11 of the present invention.

[0097] Each of the memory masters 1-1 to 1-4 outputs a request signal for requesting a right of using memory, an address signal, a read/write signal showing a type of access, a word length signal showing what word is to be accessed, a write data signal, and a data mask signal to an arbiter section 2 and receives an acknowledge signal showing acquisition of using memory and read data signal from the arbiter section 2.

[0098] The arbiter section 2 outputs a request signal, an address signal, a read/write signal, a word length signal, a write data signal, and a data mask signal selected from two or more memory masters 1-1 to 1-4 to the memory control section 3 and receives an acknowledge signal and a read data signal from the memory control section 3.

[0099] The memory control signal 3 outputs control signals of memory, that is, in the case of an SDRAM, a clock signal (CLK), a clock enable signal (CKE), a chip select signal (CS), a row address strobe signal (RAS), a column address strobe signal (CAS), a write enable signal (WE), an address signal (A), a bank address signal (BA), a data input/output signal (DQ), and a data mask signal (DQM).

[0100] The hit predicting section 4 outputs a plurality of hit prediction result to the memory control section 3. The number of hit prediction results are the same as the total number of all memories 5 and 6 being connected.

[0101] For example, if memories 5 and 6 each being made up of four banks are connected, since there exist eight banks in an entire system, the predicted number obtained as the hit prediction results becomes eight.

[0102] Each of memory masters 1-1 to 1-4, when access is to be gotten to memory, asserts a request signal and, at the same time, determines an address signal, a read/write signal, a word length signal, a write data signal, and a data mask signal.

[0103] The arbiter section 2, if only one memory master has asserted a request signal, outputs an address signal, a read/write signal, a word length signal, a write data signal, and a data mask signal fed from the one memory master to the memory control section 3 and returns an acknowledge signal and a read data signal fed from the memory control section 3 to the one memory master.

[0104] The arbiter section 2, if two or more memory masters have asserted request signals, selects one memory master out of the two or more memory masters and outputs an address signal, a read/write signal, a word length signal, a write data signal, and a data mask signal fed from the memory masters to the memory control section 3 and returns an acknowledge signal and a read data signal fed from the memory control section 3 to the memory master.

[0105] As a method for selecting one memory master from two or more memory masters, there is a method by which one memory master is selected according to predetermined priority order, a method by which one memory master being in priority order most far from time when last access is gotten is selected according to a round-robin method, and a like.

[0106] The memory control section 3, when a request signal fed from the arbiter section 2 is asserted, receives an address signal, a read/write signal, and a word length signal and produces a control signal for memory, if a read write signal indicates write access, to get write access and, if the read/write signal indicates read access, to get read access.

[0107] The memory control section 3, when write access is gotten, receives a write data signal and a data mask signal and returns, when read access is gotten, read data fed back from memory using a read data signal to the arbiter section 2.

[0108] The memory control section 3, when last data is accessed, determines whether or not a bank being presently accessed is closed by referring to a hit prediction result fed from the hit predicting section 4.

[0109] The last data denotes, for example, fourth data if a word length signal indicates that four words are to be accessed.

[0110] As a hit prediction result fed from the hit predicting section 4, an individual result is output for each bank in memory and the memory control section 3 makes reference to a hit prediction result corresponding to a bank in which last data is stored.

[0111] Moreover, the memory control section 3 determines whether a bank being presently accessed is closed by making reference not only to the last data but also to a hit prediction result fed from the hit predicting section 4 when next data is stored in a bank being different from the bank being presently accessed.

[0112]FIG. 5 is still another block diagram showing a system made up of a memory control section 3 corresponding to any one of claims 12, 13, 14, and 15 of the present invention, and a plurality of memories 5 and 6 according to the embodiment of the present invention.

[0113] The hit predicting section 4 receives a hit signal or a miss hit signal from the memory control section 3. Each of the number of hit results and miss hit results is the same as the total number of all banks in memory.

[0114] The memory control section 3, if an address used for access indicates the same page as was accessed previous time when access is started in each bank, asserts a hit signal of a corresponding bank.

[0115] Moreover, the memory control section 3, if an address used for access indicates a page being different from a page that was accessed previous time when access is started in each bank, asserts a miss hit signal of a corresponding bank.

[0116] The time when access is started includes not only time when access is first started after a request signal fed from the arbiter section 2 has been asserted but also time when access is next started if each of data having been currently accessed and data being accessed next is stored in each of different banks before access to a length of words indicated by a word length signal is completed.

[0117] The memory control section 3, in order to produce a hit signal or a miss hit signal, has to store a page that was accessed last time for each bank.

[0118] Moreover, operations of the hit predicting section 4 stated in claim 12 are in conformance with those stated in claim 2. Similarly, operations of the hit predicting section stated in claims 13, 14, and 15 are in conformance with those stated in claims 3, 4 and 5.

[0119]FIG. 6 is a block diagram showing the system made up of the memory control section 3 corresponding to claims 16 to 20 and a plurality of memories 5 and 6 according to the embodiment of the present invention.

[0120] In addition to the example corresponding to claim 11, each of memory masters outputs a next address confirmation signal indicating an address to be used when access is required next and its address signal showing that its address signal is determined to the arbiter section 2 and memory control section 3.

[0121] The memory control section 3, when last data is accessed, determines whether a bank is closed or not by making reference to a hit prediction result fed from the hit predicting section 4. At this point, if there is one or more of the memory masters that are outputting a next address confirming signal and if there is a memory master in which both the bank and the page indicated by its next address signal are matched to both the bank and the page being accessed presently, the memory control section 3 terminates its routine without closing the bank being presently accessed, regardless of a hit prediction result fed from the hit predicting section 4, and the arbiter section 2, when selecting a memory master that accesses memory next, selects a memory master in which both the bank and the page indicated by the next address signal are matched to both the bank and the page being accessed presently.

[0122] On the other hand, the memory control section 3, it there is one or more of the memory masters that are outputting a next address confirming signal and if there is a memory master in which only the bank out of the bank and the page indicated by its next address signal is matched only to the bank and the page out of the bank and the page indicated by its next address signal is not matched to the page being accessed presently, closes the bank being accessed and terminates its routine, regardless of a hit prediction result fed from the hit predicting section 4.

[0123] For example, let it be assumed that there are three memory masters 1-1, 1-2, and 1-3, that the memory master 1-1 is being presently accessed which has its last address of bank 0 and page 0. When the memory masters 1-2 and 1-3 assert a next address confirming signal and if a bank and a page indicated by the next address signal output from the memory master 1-2 is 0 and 0 respectively and, if a bank and a page indicated by the next address signal output from the memory master 1-3 is 0 and 1 respectively, the memory control section 3, regardless of a hit prediction result fed from the hit predicting section 4, terminates its routine without closing the bank 0 while the memory master 1-1 is accessing the bank and the page, and the arbiter section 2 selects the memory master 1-2 following the memory master 1-1.

[0124] The memory master 1-2 gets access to the bank 0 and page 0. However, since the bank 0 has been already opened at the page 0, the memory master 1-2 can start access immediately after the memory master 1-1 has completed its access.

[0125] If the bank 0 had been closed at time of completion of access by the memory master 1-1, memory access has to be started after the bank 0 has been made active, time is spent before next memory access is started.

[0126] Moreover, if the memory master 1-3 subsequent to the memory master 1-1 has been selected, the bank 0 has to be made active after the bank 0 has been pre-charged, time is spent before next memory access is started.

[0127] Moreover, if a bank and a page indicated by a next address signal output from the memory master 1-2 is 0 and 1 respectively and, if a bank and a page indicated by a next address signal output from the memory master 1-3 is 0 and 2 respectively, the memory control section 3, regardless of a hit prediction result fed from the hit predicting section 4, closes the bank 0 at time when the memory master 1-1 completes its access and terminates its routine.

[0128] Even if either a memory master 1-2 or a memory master 1-3 subsequent to the memory master 1-1 is selected, access is gotten to the bank 0 in memory. However, since the bank 0 is closed, after the memory master 1-1 has accessed the bank, the bank 0 can be made active and, after the bank 0 has been made active, memory can be accessed.

[0129] When the bank 0 was closed when the memory master 1-1 had completed the access, the bank 0 has to be made active after the bank 0 has been pre-charged following completion of access by the memory master 1-1 and, as a result, time is spent before memory access is started next.

[0130] Next, a concrete example of configurations of the hit predicting section 4 is described by referring to FIG. 7. FIG. 7 is a block diagram showing configurations of one bank installed in a hit predicting section corresponding to claim 5 and 15.

[0131] Moreover, the hit predicting section 4 has blocks shown in FIG. 7 being equal in number to the banks which are not shown. In addition to this, the hit predicting section 4 also has a section to receive an instruction for setting of “j-1”, “k-1”, and “m” (instruction for setting “j”, “k”, and “m”) and to hold these set values.

[0132] In FIG. 7, a hit signal/miss hit signal inputting section 41, when either of a hit signal or a miss hit signal is input, shifts a result holding shift register 42 by one bit and inputs, when a hit signal is input, a numeric code 1 indicating a hit, to bit 0 and, when a miss hit signal is input, a numeric code 0 indicating a miss hit, to bit 0 in the shift register.

[0133] A judging section 43 receives a value “k-1” from the holding circuit (section) and outputs a numeric code “1” if all bits from the bit “0” to bit “k-1” in the result holding shift register 42 are 0 (zero) and outputs a numeric code “0” if all bits from the bit “0” to bit “k-1” in the result holding shift register 42 are not 0.

[0134] The judging section 44 receives a value “j-1” from the holding circuit and outputs a numeric code “1” if all bits from the bit “0” to bit “j-1” in the result holding shift register 42 are “1” (one) and outputs a numeric code “0” if all bits from the bit “0” to bit “j-1” in the result holding shift register 42 are 0.

[0135] The judging section 45 receives an “m” value from the holding circuit and adds all bits from the bit “O” to bit “n-1” in the result holding shift register 42 and outputs, if the result of the addition is “m” or more, a numeric code “1” and outputs, if the result of the addition is not “m” or more, a numeric code 0.

[0136] A judged result outputting section 46 outputs a numeric code “0” indicating a miss hit signal if a result fed from the judging section 43 shows “1” and a numeric code “1” indicating a hit signal if the result fed from the judging section 43 shows “0” and the result fed from the judging section 44 shows “1” and a numeric code 1 if both the results fed from the judging section 43 and the judging section 44 show “0” and the result fed from the judging section 45 shows “1” and a numeric code “0” indicating a miss hit signal if all the results from the judging section 43, the judging section 44, and the judging section 45 show “0”.

[0137] As described above, if eight pieces of banks exist in an entire system, the hit predicting section 4 also has eight sets of such these circuits.

[0138] The circuit for each bank in the hit predicting section 4 stated in claim 2 and claim 12 is made up of the hit signal/miss hit signal inputting section 41, n-bit result holding shift register 42, and the judging section 45 and uses an output from the judging section 45 as a hit prediction result.

[0139] The circuit for each bank in the hit predicting section 4 corresponding to claim 3 and claim 13 is made up of a hit signal/miss hit signal inputting section 41, a maximum n-bit result holding shift register 42, and the judging section 44 and uses an output from the judging section 44 as a hit prediction result.

[0140] The circuit for each bank in the hit predicting section 4 corresponding to claim 4 and claim 14 is made up of the hit signal/miss hit signal inputting section 41, the maximum n-bit result holding shift register 42, and the judging section 43 and uses an output from the judging section 43 as a hit prediction result.

[0141] An example of timing with which the memory control section 3 controls signals to be fed to memory based on prediction of the hit predicting section 4 is described by using timecharts in FIG. 8 to FIG. 10.

[0142] The example is shown in which an SDRAM is used as memory and read access is gotten.

[0143]FIG. 8 is a timechart showing a case in which the memory access control device of the present invention, while getting read-access, predicts a hit in next access and a hit is found in access. A number sign “#” at a head of a signal name represents a signal being active LOW.

[0144] In FIG. 8, when, following access {circle over (1)}, a hit is predicted in access {circle over (2)}, no pre-charging is performed when access is completed. Since a page hit is found in next access and switching of A0 to A9 and/or issuance of a ROW active command (#RAS is made LOW) is not required, next access is gotten earlier.

[0145]FIG. 9 is a timechart showing a case in which the memory access control device of the present invention, while getting read-access, predicts a hit in next access and a miss hit is found in access.

[0146] When a hit is predicted, no pre-charge is performed at time of completion of access. If a miss hit occurs in next access, after pre-charge command (#RAS and #WE are made LOW at the same time) has been issued, issuance of the ROW active command (#RAS is made LOW) following switching of A0 to A9 to ROW address is required, next access is gotten later.

[0147]FIG. 10 is a timechart showing a case in which the memory access control device of the present invention, while getting read-access, predicts a miss hit in next access. Since a miss hit is predicted, at time of completion of access, A10 is made enabled and auto-precharge is performed.

[0148] Or, a pre-charge command (#RAS and #WE are made LOW at the same time. These are shown in dotted lines.) may be issued.

[0149] In this case, if a page hit is found in subsequent access {circle over (2)} or a miss hit is found in subsequent access {circle over (2)}, result data determining timing for access {circle over (2)} remains unchanged.

[0150] Access time is shortened to ⅔ or less when compared with a case in which a miss hit occurs after a hit is predicted.

[0151] It is apparent that the present invention is not limited to the above embodiments but may be changed and modified without departing from the scope and spirit of the invention. 

What is claimed is:
 1. A memory access control device comprising: a memory master to make a request for access to memory; a memory control unit to produce control signals of memories based on access information to be output from said memory master; and a hit predicting unit to predict whether or not next access to each bank in memory becomes access to a same page; wherein said memory control unit, when a hit predicting unit predicts that “a page hit is found” which means that “next access to said bank becomes access to a same page”, terminates its routine without closing a bank being presently accessed at time of completion of present access operations and, when said hit predicting unit predicts that “a miss hit is found” which means that “next access to said bank becomes access to a different page”, closes said bank being presently accessed at time of completion of present access operations and terminates its routine.
 2. The memory access control device according to claim 1, wherein said hit predicting unit stores results from last “n” (n is a natural number) times accesses to each bank in memory as to whether a page hit has been found or a miss hit has been found and predicts, if a number of times of accesses by which a page hit is found out of last “n” times accesses is “m” or more (m≦n: “m” and “n” are natural numbers), that a page hit is found in next access to said bank, and on the other hand predicts, if said number of times of accesses is not “m” or more, that a miss hit is found in next access to said bank.
 3. The memory access control device according to claim 1, wherein said hit predicting unit stores results from last “j” (“j” is a natural number) times accesses to each bank in memory as to whether a page hit has been found or a miss hit has been found and predicts, when a page hit has been found in all last “j” times accesses, that a page hit is found in next access to said bank, and on the other hand predicts, if no page hit has been found at least one time in all last “j” times accesses, that a miss hit is found in next access to said bank.
 4. The memory access control device according to claim 1, wherein said hit predicting unit stores results from last “k” (“k” is a natural number) times accesses to each bank in memory as to whether a page hit has been found or a miss hit has been found and predicts, if a miss hit has been found in all last “k” times accesses, that a miss hit is found in next access to said bank, and on the other hand predicts, if no miss hit has been found at least one time in all last “k” times accesses, that a miss hit is found in next access to said bank.
 5. The memory access control device according to claim 1, wherein said hit predicting unit stores results from last “n” (“n” is a natural number) times accesses to each bank in memory as to whether a page hit has been found or a miss hit has been found and predicts, when a miss hit has been always found in all last “k” times accesses (k≦n: “k” and “n” each are a natural number) out of last “n” times accesses, that a miss hit is found in next access to said bank and predicts, when no miss hit has been found at least one time in all last “k” times accesses out of last “n” times accesses, if a page hit has been always found in all last “j” times accesses (j≦n: “j” and “n” each are a natural number) out of last “n” times accesses, that a page hit is found in next access to said bank and predicts, when a miss hit has been found at least one time in all last “j” times accesses out of last “n” times accesses, if a number of times of accesses by which a page hit has been found out of last “n” times accesses is “m” times or more (m≦n: “m” and “n” each are a natural number), that a page hit is found in next access to said bank and predicts, when a number of times of accesses by which a page hit has been found out of last “n” times accesses is not “m” times or more, that a miss hit is found in next access to said bank.
 6. The memory access control device according to claim 1, wherein said memory master informs, when a bank and a page to be accessed next have been determined, said memory control unit of information about said bank and said page to be accessed and wherein said memory control unit, if said bank to be accessed next by said memory master is same as that being presently accessed and said page to be accessed by said memory master is same as that being presently accessed, terminates its routine, regardless of a prediction result from said hit predicting unit, without closing said bank being presently accessed at time of completion of present access operations and, if said bank to be accessed next by said memory master is same as that being presently accessed and said page to be accessed by said memory master is different from that being presently accessed, closes said bank being presently accessed at time of completion of present access operations, regardless of a prediction result from said hit predicting unit, and terminates its routine.
 7. The memory access control device according to claim 2, wherein said memory master informs, when a bank and a page to be accessed next have been determined, said memory control unit of information about said bank and said page to be accessed and wherein said memory control unit, if said bank to be accessed next by said memory master is same as that being presently accessed and said page to be accessed by said memory master is same as that being presently accessed, terminates its routine, regardless of a prediction result from said hit predicting unit, without closing said bank being presently accessed at time of completion of present access operations and, if said bank to be accessed next by said memory master is same as that being presently accessed and said page to be accessed by said memory master is different from that being presently accessed, closes said bank being presently accessed at time of completion of present access operations, regardless of a prediction result from said hit predicting unit, and terminates its routine.
 8. The memory access control device according to claim 3, wherein said memory master informs, when a bank and a page to be accessed next have been determined, said memory control unit of information about said bank and said page to be accessed and wherein said memory control unit, if said bank to be accessed next by said memory master is same as that being presently accessed and said page to be accessed by said memory master is same as that being presently accessed, terminates its routine, regardless of a prediction result from said hit predicting unit, without closing said bank being presently accessed at time of completion of present access operations and, if said bank to be accessed next by said memory master is same as that being presently accessed and said page to be accessed by said memory master is different from that being presently accessed, closes said bank being presently accessed at time of completion of present access operations, regardless of a prediction result from said hit predicting unit, and terminates its routine.
 9. The memory access control device according to claim 4, wherein said memory master informs, when a bank and a page to be accessed next have been determined, said memory control unit of information about said bank and said page to be accessed and wherein said memory control unit, if said bank to be accessed next by said memory master is same as that being presently accessed and said page to be accessed by said memory master is same as that being presently accessed, terminates its routine, regardless of a prediction result from said hit predicting unit, without closing said bank being presently accessed at time of completion of present access operations and, if said bank to be accessed next by said memory master is same as that being presently accessed and said page to be accessed by said memory master is different from that being presently accessed, closes said bank being presently accessed at time of completion of present access operations, regardless of a prediction result from said hit predicting unit, and terminates its routine.
 10. The memory access control device according to claim 5, wherein said memory master informs, when a bank and a page to be accessed next have been determined, said memory control unit of information about said bank and said page to be accessed and wherein said memory control unit, if said bank to be accessed next by said memory master is same as that being presently accessed and said page to be accessed by said memory master is same as that being presently accessed, terminates its routine, regardless of a prediction result from said hit predicting unit, without closing said bank being presently accessed at time of completion of present access operations and, if said bank to be accessed next by said memory master is same as that being presently accessed and said page to be accessed by said memory master is different from that being presently accessed, closes said bank being presently accessed at time of completion of present access operations, regardless of a prediction result from said hit predicting unit, and terminates its routine.
 11. A memory access control device comprising: two or more memory masters to make a request for access to memory; an arbiter unit to arbitrate memory access requests fed from said memory masters and to select access information fed from any one of said memory masters; a memory control unit to produce a control signal of memory based on access information output from said arbiter unit; and a hit predicting unit to predict whether or not next access to each bank in memory becomes access to a same page; wherein said memory control unit, when said hit predicting unit predicts that “a page hit is found” which means that “next access to said bank is access to a same page”, terminates its routine without closing said bank being presently accessed at time of completion of present access operations and when said hit predicting unit predicts that “a miss hit is found” which means that “next access to said bank is access to a different page”, closes said bank being presently accessed at time of present access operations and terminates its routine.
 12. The memory access control unit according to claim 11, wherein said hit predicting unit stores results from last “n” (“n” is a natural number) times accesses to each bank in memory as to whether a page hit has been found or a miss hit has been found and predicts, if a number of times of accesses by which a page hit is found out of last “n” times accesses is “m” or more (m≦n: “m” and “n” each are a natural number), that a page hit is found in next access to said bank and predicts, if said number of times of accesses is not “m” or more, that a miss hit is found in next access to said bank.
 13. The memory access control device according to claim 11, wherein said hit predicting unit stores results from last “j” (“j” is a natural number) times accesses to each bank in memory as to whether a page hit has been found or a miss hit has been found and predicts, when a page hit has been found in all last “j” times accesses, that a page hit is found in next access to said bank and predicts, if no page hit has been found in all last “j” times accesses, that a miss hit is found in next access to said bank.
 14. The memory access control device according to claim 11, wherein said hit predicting unit stores results from last “k” (“k” is a natural number) times accesses to each bank in memory as to whether a page hit has been found or a miss hit has been found and predicts, if a miss hit has been found in all last “k” times accesses, that a miss hit is found in next access to said bank and predicts, if no miss hit has been found in all last “k” times accesses, that a page hit is found in next access to said bank.
 15. The memory access control device according to claim 11, wherein said hit predicting unit stores results from last “n” (“n” is a natural number) times accesses to each bank in memory as to whether a page hit has been found or a miss hit has been found and predicts, when a miss hit has been found in all last “k” (k≦n: “k” and “n” each are a natural number) times accesses out of last “n” times accesses, that a miss hit is found in next access to said bank and predicts, when no miss hit has been found at least one time in all last “k” times accesses out of last “n” times accesses, if a page hit is found in all last “j” times accesses (j≦n: “j” and “n” each are a natural number) out of last “n” times accesses, that a page hit is found in next access to said bank and predicts, when a miss hit has been found at least one time in all last “j” times accesses out of last “n” times accesses, if a number of times of accesses by which a page hit has been found out of last “n” times accesses is- “m” times or more (m≦n: “m” and “n” each are a natural number), that a page hit is found in next access to said bank and predicts, when a number of times of accesses by which a page hit has been found out of last “n” times accesses is not “m” times or more, that a miss hit is found in next access to said bank.
 16. The memory access control device according to claim 11, wherein each memory master informs, when a bank and a page to be accessed next have been determined, said arbiter unit and said memory control unit of information about said bank and said page to be accessed and wherein said memory control unit, if there exists said memory master which gets next access to a same bank as that being presently accessed and to a same page as that being presently accessed, terminates its routine without closing said bank being presently accessed at time of completion of present access operations, regardless of a prediction result fed from said hit predicting unit, and terminates its routine and, if there exists said memory master which gets next access to a same bank as that being presently accessed and to a page being different from that being presently accessed, closes said bank being presently accessed at time of completion of present access operations, regardless of a prediction result fed from a hit predicting unit, and terminates its routine and said arbiter unit, if there exists said memory master which gets next access to a same bank and a same page as those being presently accessed, selects said memory master with priority.
 17. The memory access control device according to claim 12, wherein each memory master informs, when a bank and a page to be accessed next have been determined, said arbiter unit and said memory control unit of information about said bank and said page to be accessed and wherein said memory control unit, if there exists said memory master which gets next access to a same bank as that being presently accessed and to a same page as that being presently accessed, terminates its routine without closing said bank being presently accessed at time of completion of present access operations, regardless of a prediction result fed from said hit predicting unit, and terminates its routine and, if there exists said memory master which gets next access to a same bank as that being presently accessed and to a page being different from that being presently accessed, closes said bank being presently accessed at time of completion of present access operations, regardless of a prediction result fed from a hit predicting unit, and terminates its routine and said arbiter unit, if there exists said memory master which gets next access to a same bank and a same page as those being presently accessed, selects said memory master with priority.
 18. The memory access control device according to claim 13, wherein each memory master informs, when a bank and a page to be accessed next have been determined, said arbiter unit and said memory control unit of information about said bank and said page to be accessed and wherein said memory control unit, if there exists said memory master which gets next access to a same bank as that being presently accessed and to a same page as that being presently accessed, terminates its routine without closing said bank being presently accessed at time of completion of present access operations, regardless of a prediction result fed from said hit predicting unit, and terminates its routine and, if there exists said memory master which gets next access to a same bank as that being presently accessed and to a page being different from that being presently accessed, closes said bank being presently accessed at time of completion of present access operations, regardless of a prediction result fed from a hit predicting unit, and terminates its routine and said arbiter unit, if there exists said memory master which gets next access to a same bank and a same page as those being presently accessed, selects said memory master with priority.
 19. The memory access control device according to claim 14, wherein each memory master informs, when a bank and a page to be accessed next have been determined, said arbiter unit and said memory control unit of information about said bank and said page to be accessed and wherein said memory control unit, if there exists said memory master which gets next access to a same bank as that being presently accessed and to a same page as that being presently accessed, terminates its routine without closing said bank being presently accessed at time of completion of present access operations, regardless of a prediction result fed from said hit predicting unit, and terminates its routine and, if there exists said memory master which gets next access to a same bank as that being presently accessed and to a page being different from that being presently accessed, closes said bank being presently accessed at time of completion of present access operations, regardless of a prediction result fed from a hit predicting unit, and terminates its routine and said arbiter unit, if there exists said memory master which gets next access to a same bank and a same page as those being presently accessed, selects said memory master with priority.
 20. The memory access control device according to claim 15, wherein each memory master informs, when a bank and a page to be accessed next have been determined, said arbiter unit and said memory control unit of information about said bank and said page to be accessed and wherein said memory control unit, if there exists said memory master which gets next access to a same bank as that being presently accessed and to a same page as that being presently accessed, terminates its routine without closing said bank being presently accessed at time of completion of present access operations, regardless of a prediction result fed from said hit predicting unit, and terminates its routine and, if there exists said memory master which gets next access to a same bank as that being presently accessed and to a page being different from that being presently accessed, closes said bank being presently accessed at time of completion of present access operations, regardless of a prediction result fed from a hit predicting unit, and terminates its routine and said arbiter unit, if there exists said memory master which gets next access to a same bank and a same page as those being presently accessed, selects said memory master with priority. 